Study: A scanlet for testing and updating designs intended for the verification of fuzzy logic controllers
DOI:
https://doi.org/10.21754/tecnia.v10i2.466Keywords:
Scanlet, ATPG, JAVA API for Boundary-Scan, Fuzzy Logic, Functional VerificationAbstract
This article presents preliminary work on the implementation of a Scanlet for: (a) automatic checking of pattern generation related to digital circuits based on a
model with interruption in the presence of failure, (b) in situ monitoring and debugging, (c) update of
the architecture of a fuzzy logic controller, and (d) pin-level fault injection using Java
API. Points (a)-(c) are verification tasks. As a first approximation, the STUD system has been developed using the (built-in) JTAG (Joint Test Action Group) architecture and configured by a CPLD for testing and programming operations. Meanwhile, the operations are executed by Scanlet, which can be run from an Internet page. Finally, a fuzzy logic controller, like an IP core, is used as a trademark.
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